1. Technical Field
The present disclosure relates to a method for verifying the alignment between integrated electronic devices.
2. Description of the Related Art
There are available techniques that enable stacking of a number of integrated electronic circuits (“chips”), in such a way as to form a so-called three-dimensional structure, with evident benefits in terms of reduction of the space occupied by the chips; these techniques are commonly known as 3D stacking and are preparatory to the achievement of the so-called 3D packaging, i.e., of the three-dimensional structures.
Within single three-dimensional structures, it is moreover possible to connect the chips contained therein in such a way as to enable exchange of signals between the chips themselves. For this purpose, it is possible to resort to systems of communication between chips, i.e., communications systems that enable communications of a so-called “inter-chip” type, thanks to the presence of a coupling between two or more chips. The coupling can be of a so-called “contact” type, i.e., of an ohmic type, in which case it can be implemented by one or more of the following: through silicon vias (TSVs), bumps, pillar bumps, etc. Alternatively, the coupling can be of a so-called “contactless” type, i.e., for example, of an inductive or capacitive type.
Irrespective of the coupling type, in order to optimize the communications between the chips present in a given three-dimensional structure, it is important for the chips to be properly stacked to form the three-dimensional structure. In fact, a possible misalignment between two or more chips, may not only prevent a correct packaging of the three-dimensional structure, but may also involve a reduction in the possibility of carrying out communications between the chips of the three-dimensional structure, given that the corresponding couplings may be damaged on account of misalignment.
By way of example, FIG. 1 shows a misalignment within a structure formed by a first chip IC1 and a second chip IC2, for example, introduced during the packaging (or stacking) of the first and second chips IC1, IC2. In practice, with respect to the reference system x, y, z shown in FIG. 1, the first chip IC1 is translated with respect to the second chip IC2 by a deviation Δx along the axis x of the reference system x, y, z. In addition, whereas the second chip IC2 is correctly aligned to the reference system x, y, z, i.e., it has respective principal axes x″, y″, z″ aligned with the corresponding axes of the reference system x, y, z, the first chip IC1 is rotated by an angle φ with respect to the reference system x, y, z, and hence is tilted by the angle φ with respect to the second chip IC2. In particular, the first chip IC1 has respective principal axes x′, y′, z′, and the axes x′ and z′ are rotated by the angle φ with respect to the axes x and z, respectively. This rotation contributes to the misalignment between the first chip IC1 and the second chip IC2. In a similar way, the first chip IC1 can likewise be rotated with respect to the second chip IC2 by an angle θ (not shown), formed by the plane defined by the axes y′ and z′ and by the plane defined by the axes y″ and z″.
In a way similar to what has been described in regard to the chips, techniques enable stacking of a number of dice, where by “die” is meant the result of the step of “dicing” commonly used in the processes of formation of the die. In practice, it is today possible to obtain three-dimensional structures formed by a number of dice, in a way similar to what was previously possible with chips alone.
Also for the three-dimensional structures formed by dice, the misalignment between two or more dice may entail the impossibility of packaging correctly the three-dimensional structures, in addition to the reduction in the possibility of carrying out communications between the dice, which are uncoupled on account of the misalignment.
In order to detect the presence of a misalignment, techniques are available that envisage the use of markers, which are set on the chips/dice. Appropriate optical detectors determine the positions of the optical markers; subsequently, the positions determined are processed in such a way as to verify the alignment of the chips/dice.
The techniques based upon the use of markers enable verification of the alignment of the chips/dice with high precision; however, they are particularly costly and complex given that they require the use of optical detectors.
Furthermore, different techniques exist, which envisage coupling, by means of appropriate capacitors, the chips, alignment of which is to be verified, and detecting the presence of possible misalignments on the basis of signals transmitted and received on the electrodes of these capacitors, as described, for example, in the U.S. Patent Publication No. US2002/0191835, or else in the U.S. Patent Publication No. US2007/0067115. These techniques are, however, subject to the limits intrinsically associated to determination of the values of capacitance of the capacitors; hence, they do not enable detection of misalignments in a particularly precise way.